Adding Cooling Capacity to SCD Substrates: Microchannels, etc.

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Adding Cooling Capacity to SCD Substrates: Microchannels, etc.

Cooling capacity and SCD multiply

The extent of system-level value captured by SCD depends upon downstream cooling at the base of the thermal stack. In DF’s model, SCD enables 2.1× higher permissible power at 50 kW/m²K and scales to 3.1× at 100 kW/m²K, 4.3× at 200 kW/m²K and 5.0× at 300 kW/m²K. Conventional silicon reaches only 1.37× at 300 kW/m²K because localized heat flux inside the die remains a bottleneck.

The curve shows why cooler performance matters after hotspot spreading. It does not assign a demonstrated HTC to a particular jet array, vapor chamber or microchannel product.

Modeled permissible power versus cooling coefficient for SCD and silicon, using a common silicon baseline.
Modeled permissible power versus heat-transfer coefficient (HTC) at the package interface. Coolant inlet: 45°C; peak junction limit: 105°C. All ratios use the same 675 W silicon baseline at 50 kW/m²K.

These advanced cooling approaches represent additional system level upside. They are not required for the initial SCD substrate business case.

Advanced Cooling explains how SCD prepares a hotter, more uniform surface for heat removal. The next decision is how to add cooling capacity while keeping the package robust and the cooling system practical to operate.

Microchannels need a robust substrate

At DF, we view microchannels as an unnecessarily complex route to cooling SCD substrates.

Direct jet impingement on diamond offers better thermal performance and operational robustness with a simpler architecture.

Highly integrated silicon circuitry needs a robust substrate. One can’t simply have all that advanced silicon transistor circuitry live on a foil one quarter the thickness of a piece of paper. The application of microchannels is therefore one for behind a robust substrate, rather than digging lots of channels right below transistors.

Microchannels suffer from a great by-design shortcoming: the liquid becomes hotter as it flows along a channel. (This is where jet impingement arrays with distributed return are architecturally superior.)

Microchannels imply operational and financial risk

A viable data center cooling solution must be operationally robust and financially risk-adjusted. High heat-transfer capability alone does not meet that requirement. Microchannels bring liquid close to the transistor layer, but also introduce channel fabrication, fluid manifolds, pressure drop, pumping energy, fouling, clogging, leakage, electrical isolation, flow instability and long-term serviceability challenges.

At chip fabs, ultrapure water is available from major industrial systems with disciplined continuous monitoring. Data centers use much simpler water-treatment systems and less stringent controls. Assuming chip-fab standards in a facility that was never designed to deliver them is a cooling-system design error.

The extremely small channels are highly susceptible to clogging from even tiny particles, such as dust, debris, or manufacturing residues. This can severely reduce efficiency, lead to localized overheating (hot spots), and potentially cause system failure. Designing systems with prevention, detection, and remediation in mind is essential for applications that run 24/7.

A single leak could destroy the chip; maintaining hermetic seals under pressure and temperature cycling is nontrivial. The intricate design with numerous small channels and sealed joints can increase the risk of leaks, especially if manufacturing tolerances are not met or if the system experiences thermomechanical stress.

Microchannel systems require heat exchangers and pumps designed for much higher pressure drops, and tighter flow uniformity control than traditional cold plate systems. These specialized heat exchangers are harder to inspect, clean, or repair if damaged or clogged.

Microchannels behind diamond?

Microchannels are simplified if they are used in combination with SCD substrates. They are an avenue to heat removal that can work well together with, and complement, SCD substrating. In lieu of just bonding SCD to a chip die, a SCD/Si sandwich is bonded, and then a microchannelled Si wafer is further bonded to the SCD’s thin Si. This yields a near optimal thermal resistance stack that nearly optimally combines hotspot spreading and cooling. Combining microchannels with SCD can help with enabling chip recoverability after facility incidents such as particle contaminations.

The Winner: Direct jet impingement on SCD

DF’s SCD substrate is a solid-state component and contains no fluid path. This provides an attractive reliability distinction. SCD can also be combined with external jet or spray cooling, preserving accessibility and serviceability of the coolant system while providing near-junction heat spreading inside the package.

Direct liquid cooling of SCD substrates uses the stand-out thermal conductivity of SCD twice: at the frontside for transistor hotspots, and at the backside for simplifying the number and kind of jets required.

By laterally distributing heat at the coolant interface, SCD reduces local dryout risk and allows fewer or larger liquid jets than would be practical on a poorly spreading surface. Distributed return outlets also address the channel-heating problem described above.